Physical Design Lead/Manager

• • • Own and drive the physical implementation of next-generation Mixed-Signal SOC with HS ADC/DAC, HS interfaces like PCIe, LPDDR, MIPI, USB2/3, Gig Ethernet etc.
    • Understand the requirements and define physical implementation methodologies.
    • Collaborate with architecture, design, front end and CAD teams to deliver high-quality physical designs.
    • Implement and verify designs at all levels of hierarchy in the SOC.
    • Interact with foundry over matters of technology, schedule, and signoff

Qualifications and Experience

• • • 8+ years of experience of physical design in SOCs.
    • 3+ years of experience in managing projects and leading teams.
    • Hands-on expertise in all of the following areas
  • o Floorplanning
  • o Power planning
  • o Implementation of UPF Methodology
  • o Logic and clock tree synthesis
  • o Placement
  • o Timing Closure
  • o Routing
  • o Extraction
  • o Physical Verification (DRC & LVS),
  • o Crosstalk Analysis
  • o EM/IR
  • • Full chip/ top-level expertise in multiple chip tape-outs.
    • Good understanding and experience in SCAN, BIST, and ATPG.
    • Strong background in TCL/Perl/Python programming is a must.
    • Expertise in double patterning process nodes is desirable. Experience with sub 40 nM nodes required
    • Expertise in Cadence or Synopsys RTL-to-GDSII flow is preferred.

Expectations

• • Do the FC Floor Plan and Layout
  • Set up the EDA tools and develop the scripts
  • Develop the UPF methodology
  • Implement the Power, Clock Grid
  • Generate the SDF files
  • Do the DRC, ERC, LVS, SI and Cross talk checks, Do the DFM checks
  • Tapeout the chip
  • Manage and mentor the PD and custom layout team
  • Make changes, as needed to the custom layout of the IP
  • Release the GDS2 to the Fabs