Principal Design Engineer
GatedTalent - Connecting Top Executive Search Firms And Executives
Date: 3 weeks ago
City: Hyderabad
Contract type: Full time
Job responsibilities:
BE/BTECH/ME/MTECH Or Equivalent Degree
RESPONSIBILITIES:
#JPKR
BE/BTECH/ME/MTECH Or Equivalent Degree
RESPONSIBILITIES:
- Develop test plans, tests , and verification infrastructure for complex IP’s/sub-system/SOC’s.
- Create verification environment using UVM methodology.
- Create reusable bus functional models, monitors, checkers, and scoreboards.
- Drive functional coverage driven verification closure.
- Work with architects, designers and DFT teams.
- BTech/ MTech with 10-14 years of experience.
- IP/Sub-system/SOC level verification experience.
- Expert in developing test bench/test case using System Verilog & UVM.
- Experience in leading verification closure of complex IP/SOC for at least one project.
- Experience with code coverage, functional coverage & assertions is desired.
- Experience in at least one of the following areas:
- CPU verification
- Memory controller verification
- DDR Protocol – DDR4, DDR5, LPDDR4 and LPDDR5
- USB 2 and USB 3 protocol
- PCIE
- Bus protocols (AXI/AHB/APB)
- Exposure to industry standard verification tools for simulation and debug
- Good debugging and problem-solving skills.
- Good communication skills
#JPKR
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