Associate II - VLSI STA NT

2 - 3 Years 1 Opening Hyderabad

Role description

Role Proficiency:

Execute any internal project or small tasks of customer project in any field of VLSI Frontend Backend or Analog design under minimal supervison from the Lead

Outcomes:

• As an Individual contributor work on any one task of RTL Design/Module in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc.

• Analyse and complete the assigned task in the defined domain(s) successfully on-time with minimal support from senior engineers

• Ensure quality delivery as approved by the senior engineer or project lead

Measures of Outcomes:

• Quality –verified using relevant metrics by Lead/Manager

• Timely delivery - verified using relevant metrics by Lead/Manager

• Reduction in cycle time and cost using innovative approaches

• Number of trainings attended

Outputs Expected:

Quality of the deliverables:

• Clean delivery of the module in-terms of ease in integration at the top level

• Ensure functional spec / design guidelines are met 100% of the time without deviation or limitation

• Documentation of the tasks and work performed

Timely delivery:

• Meet project timelines as given by the team lead/program manager

• Help with intermediate tasks delivery by other team members to ensure progress

Teamwork:

• Teamwork participation; supporting team members in the time of need

• Able to perform additional tasks in case of any team member(s) is not available

Innovation & Creativity:

• Pro-actively plan approach towards repeated work by automating tasks to save design cycle time

• Participation in technical discussion
  training
  forum

Skill Examples:

• Languages and Programming skills:a. System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice (any one)

• EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (any one)

• Technical Knowledge: (any one)a. Understands IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Knows Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec. Good knowledge of Physical Design / Circuit Design / Analog Layout d. Good understanding of Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione. Knowledge in Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design

• Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below

• Required technical skills and prior design knowledge to execute assigned tasks

• Ability to learn new skills in case required technical skills are not present to a level needed to execute the project

• Able to deliver tasks with quality and 100% on-time per quality guidelines and GANTT

• Strong communication skills

• Good analytical reasoning and problem-solving skills with attention to detail

Knowledge Examples:

• Previous project experience in any of the design by executing any one of the following RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc.
  • Good Understanding of the design flow and methodologies used in designing
  • Understand the assigned tasks and have sufficient knowledge to execute the project tasks assigned by the client / manager per skill set
  
  
  Additional Comments:

  Required Primary Key skills – STA, nano time Job Description: You will be part of a Physical Design / Timing Closure team for projects with GHz freq range and cutting-edge technologies. You will develop timing constraints for full chip or block level and be responsible for STA signoff for a complex multi-clock, multi-voltage SoCs. You will be responsible for Synthesis, Timing Analysis (STA), CTS at Full Chip or block level for Lower tech node ( Below 14nm) Desired Skills and Experience: B. Tech. / M. Tech. with 2-8 years of experience in Synthesis, STA Expertise in synthesis of complex SoCs at block/top level and writing timing constraints for complex designs with multiple clocks and multiple voltage domains Worked on pre and post layout timing analysis and resolving the issues Expertise on post layout timing closure for multiple tape outs, including timing ECOs and STA signoff Expertise in I/O constraints developments for Industry standard protocols (e.g. DDR1/2/3, SDR, LPDDR, Flash, SPIs, Ethernet, USBHS, USBFS, JTAG, Display etc...) Hands-on experience of working on technology nodes like 28nm, 20nm, 14nm, 10nmGood knowledge of EDA tools from RC, DC, PT, PTSI Experience in formal verification RTL-to-netlist and netlist-to-netlist with DFT constraints Good knowledge of VLSI process and device characteristics Good understanding of deep submicron parasitic effects, crosstalk effects etc.TCL, perl scripting

Skills

Vlsi,Tlc,Perl

About UST

UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.